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800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

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8 Author(s)
Gillingham, P. ; Conversant Intellectual Property Manage., Inc., Ottawa, ON, Canada ; Chinn, D. ; Choi, E. ; Jin-Ki Kim
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A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP.

800MB/s DDR NAND Flash Memory Multi-Chip Package Internal Architecture. 800MB/s DDR NAND Flash Memory Multi-Chip Package Internal Architecture.

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Access, IEEE  (Volume:1 )
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