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A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion

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9 Author(s)
Takemoto, T. ; Central Res. Lab., Hitachi, Tokyo, Japan ; Yamashita, H. ; Yuki, F. ; Masuda, N.
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A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver can convert 10x 6.25-Gb/s electrical signals to 4x 25-Gb/s optical signals with 25% redundancy that improves resilience against possible laser diode (LD) failure. To alleviate degradation of the optical link due to power-supply variations, a power-supply-noise-tolerant 25-Gb/s analog FE (consisting of a TIA with a noise canceller and a fully differential LD driver) is proposed. The noise canceller can keep the power-supply variation below 0.2 mV at frequencies down to 1 MHz, and the fully differential LD driver can keep power-supply current variation below 0.64 mApp/ch, despite a large modulation current of 20 mApp. As for the transmission performance of the transceiver, eye diagrams experimentally confirmed 25-Gb/s and 6.25-Gb/s data-transmission rates. A 25-Gb/s optical-link test on the transceiver demonstrated error-free operation at -6.1-dBm OMA. Moreover, an image-transfer test on the transceiver operating at a data rate of 20 Gb/s through a 100-m multi-mode fiber was demonstrated. Total power consumption of the transceiver (including optics) was 2.2 W at full-channel operation.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:49 ,  Issue: 2 )