Super-Resolving IC Images With an Edge-Preserving Bayesian Framework

Imaging system is one of important components in integrated circuit (IC) packaging, such as flip chip and wafer level packaging. The limit of resolution in the imaging system and the defocus blur by the sensitivity of depth of field, increasingly are the new stumbling block in the pace of package technique keeping up with IC fabrication. The goal of this work is to introduce the potential of image super-resolution (SR) technique in conquering the aforementioned challenges, and facilitates detecting position mark, defect identification and other corresponding post-process applications. An edge-preserving super-resolution Bayesian framework based on total variation regularization is employed. An accurate and efficient motion estimation method is first used to assure the success of SR technique. Mathematically, the convexity of cost function guaranteeing the global optimal solution is demonstrated, and then, the steepest gradient descent for optimizing cost function is reasonably obtained. Eventually, the simulated and real experiments figure out the encouraging performance of the proposed framework that increases certainly the resolution, to the great extent eliminates the defocus blur, and could be considerable robust against the variation of blur and noise level. It is believed that the SR technique for image data processing in the IC package should open a new perspective of coping with technology challenge.