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A study of hot-carrier effects (HCE) on the 180-nm CMOS device lifetime has been performed at 300 K and 77 K for Liquid Argon Time Projection Chamber (LAr TPC). Two different measurements were used: accelerated lifetime measurement under severe electric field stress by the drain-source voltage Vds, and a separate measurement of the substrate current as a function of 1/Vds. The former verifies the canonical very steep slope of the inverse relation between the lifetime and the substrate current, and the latter confirms that below a certain value of Vds a lifetime margin of several orders of magnitude can be achieved for the cold electronics TPC readout. The low power ASIC design for LAr TPC falls naturally into this domain, where hot-electron effects are negligible. Lifetime of digital circuits (ac operation) is extended by the inverse duty factor 1/(fclockteff) compared to dc operation. This factor is large (> 100) for deep submicron technology and clock frequency needed for TPC readout. As an additional margin, Vds may be reduced by ~ 10%. Extremely low failure rate (incidence) in previous large experiments demonstrates that surface mount circuit board technology withstands very well even multiple abrupt immersion in liquid nitrogen applied in board testing, and that the total failure incidence in continuous operation over time is very low.