A single event transient hardening circuit design technique based on strengthening

In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which seriously affect the system's operation. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on logic circuits. This design style achieves SET mitigation by Strengthening the sensitive node using a likeness to feedback techniques. We have analyzed several techniques from hardening radiation at transistor level to a single event transient in 7nm FinFET devices. Simulation results have shown the proposed method has higher soft error robustness than the existing ones.