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Reducing overheads in distributed shared memory systems

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4 Author(s)
Morris, J. ; Dept. of Electr. & Electron. Eng., Western Australia Univ., Nedlands, WA, Australia ; Gregg, R.R. ; Herbert, D. ; McCoull, J.

Shared memory machines have two major overheads: keeping caches coherent and managing the multiple threads of computation which enable tolerance of very long memory latencies. Thetis is a hybrid architecture providing both shared memory and efficient message passing; it will be built from `commodity' components and consists of sites with a small number of computation processors and a separate, programmable, auxiliary processor. The auxiliary processor performs overhead tasks, e.g. maintenance of cache directories, management of memory and thread queues; placed on its own bus, it does not block or delay memory accesses from computation processors which are not waiting for it. We describe how the use of a threaded variant of C (which has a functional style) enables the run-time system to dynamically determine coherence needs-dramatically reducing the overhead of maintaining coherent caches in a shared memory machine

Published in:

System Sciences, 1997, Proceedings of the Thirtieth Hawaii International Conference on  (Volume:1 )

Date of Conference:

7-10 Jan 1997

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