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A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity

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6 Author(s)
Yuichi Miyahara ; Asahi Kasei Microdevices, Atsugi, Japan ; Mitsuhiro Sano ; Kazuo Koyama ; Toshikazu Suzuki
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Opamp gain and nonlinearity are adaptively cancelled in a pipelined ADC that features global zero-forcing LMS feedback. Two unique circuit concepts are incorporated into the design. One is a programmable gain element that adjusts the opamp gain and nonlinearity error, and the other is a digitally implemented oversampling quantizer that detects the error polarity with high precision. The total opamp-induced error is removed using an opamp input error monitoring algorithm, which also eliminates the opamp noise and offset. The proposed nonlinearity-cancelled bottom-plate sampling helps to realize accurate inter-stage residue transfer and to alleviate the stringent requirement in the design of high-gain wideband opamps. A 60 MS/s pipelined ADC is prototyped in 0.18 μm CMOS. The chip exhibits a 14b INL with a 91 dB SFDR at 1.6 V using a plain un-cascoded two-stage opamp.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:49 ,  Issue: 2 )