By Topic

Data Mining for Optimizing IC Feature Designs to Enhance Overall Wafer Effectiveness

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chen-Fu Chien ; Dept. of Ind. Eng. & Eng. Manage., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chia-Yu Hsu

As global competition continues to strengthen in semiconductor industry, semiconductor companies have to continuously advance manufacturing technology and improve productivity to maintain competitive advantages. Die cost is significantly influenced by wafer productivity that is determined by yield rate and the number of gross dies per wafer. However, little research has been done on design for manufacturing and productivity enhancement through increasing the gross die number per wafer and decreasing the required shot number for exposure. This paper aims to propose a novel approach to improve overall wafer effectiveness via data mining to generate the optimal IC feature designs that can bridge the gap between integrated circuit (IC) design and wafer fabrication by providing chip designer with the optimal IC feature size in the design phase to increase gross dies and reduce the required shots. An empirical study was conducted in a leading semiconductor company for validation. The results have shown that the proposed approach can effectively enhance wafer productivity. Indeed, the developed solution has been implemented in the company to provide desired IC features to IC designers to enhance overall wafer effectiveness.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:27 ,  Issue: 1 )