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Runtime power reduction capability of the IBM POWER7+ chip

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10 Author(s)
M. S. Floyd ; IBM Systems and Technology Group, Austin, TX, USA ; A. Drake ; N. S. Schwartz ; R. W. Berry
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Four new energy management features in the POWER7+™ chip enable larger reductions in chip power consumption and further increase energy efficiency of the system during runtime compared with prior POWER7® systems. First, per-core power gating reduces idle power consumption by allowing the system to turn off the voltage to the processor cores when they are not being used. Second, real-time measurement and control of operational guardband allows for higher maximum clock frequency as well as better dynamic voltage selection to reduce power. Third, per-thread utilization counters enable the firmware to sense processor utilization on a finer granularity and set per-core frequency targets with greater accuracy. Finally, a per-core memory access counter allows firmware to more accurately account for power consumption and budget it on a per-processor core basis. These hardware capabilities together enable new EnergyScale™ firmware functions that include voltage optimization to achieve higher turbo frequencies under stressful environmental conditions, automated idle state detection and management, per-core adaptive frequency scaling, and online power modeling for real-time estimation of energy savings.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:57 ,  Issue: 6 )