True hardware random number generation implemented in the 32-nm SOI POWER7+ processor

This paper provides a description of the hardware random number generator that is implemented on the IBM POWER7+™ processor. We discuss the underlying mechanism using basic ring oscillator circuits implemented in standard digital logic circuits. The source of entropy is based on sampling phase jitter in the ring oscillators, and the rate of phase jitter accumulation is measured. We show that the design is simple and robust yet able to generate a high rate of random bits while using a minimum of logic area. The design is very resistant to physical manipulation, being able to produce solid entropy values under environmental conditions that exceed the requirements of the surrounding circuitry. With a design-specific mechanism to correct for ring oscillator sample bias, the output shows a very high rate of entropy, which is validated.