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A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance

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6 Author(s)
Kyle Craig ; Department of Electrical Engineering, University of Virginia, Charlottesville, Virginia, USA ; Yousef Shakhsheer ; Saad Arrabi ; Sudhanshu Khanna
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This paper presents a 32 b, 90 nm data flow processor capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at the component level with rapid V DD switching and V DD dithering for near-ideal quadratic dynamic energy scaling from 0.25 V-1.2 V. This is the first full processor with Panoptic (all-inclusive) DVS, single clock cycle V DD switching, V DD dithering, and the ability to switch between high performance DVS operation and a sub-threshold mode of operation. This paper also explores V DD header switching and voltage selection considerations for additional savings. Measurements show up to 80% and 43% energy savings of using PDVS over single V DD ( SVDD) and multi- V DD ( MVDD), respectively. Additionally, PDVS shows area savings of up to 65% over MVDD given the same energy consumption.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:49 ,  Issue: 2 )