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High performance hardware architecture for multi-mode 1-D forward transform of HEVC

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2 Author(s)
Kihyun Kim ; Grad. Sch. of Inf. & Commun., Hanbat Nat. Univ., Daejeon, South Korea ; Kwangki Ryoo

This paper suggests an HEVC 1-D forward transform hardware architecture that supports four TU sizes (4×4, 8×8, 16×16, and 32×32) and yields high throughput. In the proposed transform hardware architecture, coefficient multiplication is required for all TU sizes using a common computation unit equipped with a shifter and adder. Based on the synthesis results using the TSMC 180nm CMOS process and on video of QFHD, maximum operation frequency is 400MHz. The proposed transform can achieve a high throughput rate of 10-Gpels/cycle with 159k of gate area. In addition, it treats all the TU sizes of 4×4, 8×8, 16×16, and 32×32 in 38 cycles equally.

Published in:

2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)

Date of Conference:

1-4 Oct. 2013