Skip to Main Content
The nano-scale 3-D interconnects available in monolithic 3-D integrated circuit (IC) technology enable ultrahigh density device integration at the individual transistor level. In this paper, we investigate the benefits and challenges of monolithic 3-D integration technology for ultrahigh density logic designs. We first build a 3-D standard cell library for transistor-level monolithic 3-D ICs and model their timing and power characteristics. Then, we explore various interconnect options for monolithic 3-D ICs that improve design quality. Next, we build timing-closed, full-chip GDSII layouts and perform sign-off iso-performance power comparisons with 2-D IC designs. Based on layout simulations, we compare important design metrics such as area, wirelength, timing, and power consumption of transistor-level monolithic 3-D designs with traditional 2-D, gate-level monolithic 3-D, and TSV-based 3-D designs.