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As modern electrical and optical communication systems transition toward advanced modulation schemes, there exists a pressing need for power efficient A/D converters operating at tens of gigasamples per second. Within this context, this tutorial will cover relevant circuit-and architecture-level design techniques for high-speed CMOS A/D converters. At the circuit level, we will discuss fundamental challenges in the design of track-and-hold circuits and voltage comparators, which will also include a review of clock jitter and metastability. At the architecture level, we consider tradeoffs in the design of time-interleaved SAR and flash converters as well as techniques for the estimation, system-level budgeting and calibration of circuit imperfections.