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How to transform an architectural synthesis tool for low power VLSI designs

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4 Author(s)
Gailhard, S. ; LESTER-UBS Lab., France ; Julien, N. ; Diguet, J.P. ; Martin, E.

High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different “commercial” tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented

Published in:

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Date of Conference:

19-21 Feb 1998