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A new full adder cell for low-power applications

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2 Author(s)
Shams, A.M. ; Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA ; Bayoumi, M.A.

A new low power CMOS 1-bit full adder cell is presented. It is based on recent design of XOR and XNOR gates, and pass-transistors, it has 17 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors) and the low power adder cell (14 transistors). The new cell has no short circuit power and lower dynamic power (than the other adder cells), because of less number and magnitude of circuit capacitances. It consumes 10% to 15% less power than the other two cells. A comparative analysis (using Magic and Hspice) for 8-bit ripple carry and carry select adders shows that the adders based on the new cell can save up to 25% of power consumption

Published in:

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Date of Conference:

19-21 Feb 1998

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