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A bootstrapped NMOS charge recovery logic

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2 Author(s)
Seung-Moon Yoo ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Sung-Mo Kang

This paper describes a new bootstrapped NMOS charge recovery logic (BNCRL) which realizes low energy computation. Power comparison with a state-of-the-art adiabatic charge recovery circuit is shown for an inverter chain and an 8-bit adder. The new logic circuits exhibit full rail-to-rail logic swing, less dependency of energy consumption on output load capacitance variations, and significant energy saving. Benchmark circuits were designed for comparison using 0.6-μm CMOS technology

Published in:

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Date of Conference:

19-21 Feb 1998