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This paper deals with the design and evaluation of novel dynamic random access memory (DRAM) cells that have an oxide-based resistive element added for non-volatile operation. Two existing DRAM cells (namely the 3T1D and B3T cells) are utilized as volatile cores; a RRAM circuitry (consisting of an access control transistor and an oxide resistive RAM) is added to the core to extend its operation for non-volatile operation; two NVDRAM cells are then proposed. Considerations, such as the threshold voltage for the refresh operation and output read circuitry, are also considered. The impacts of the non-volatile circuitry as well as the DRAM core selection are assessed by HSPICE simulation. Figures of merit as related to performance, process variability, power consumption, and circuit design (critical charge and area of cell layout) are established for both volatile and non-volatile DRAM cells as well as memory arrays.