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Ultra low-supply voltage reference generator with low sensitivity to PVT variations

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3 Author(s)
Hande Vinayak Gopal ; Department of Electrical Engineering, IIT-Bombay, Mumbai, India ; Prafful Gupta ; Maryam Shojaei Baghini

Majority of trim-less PVT insensitive voltage reference generators are limited to minimum supply voltage above 0.7 V. This delimits use of energy harvesting techniques in CMOS circuits and systems. This paper proposes a low-cost CMOS voltage reference, which steps up the supply voltage by charge-pump based voltage booster. The raised voltage helps to drive a traditional parasitic BJT based bandgap voltage reference. The proposed voltage reference scheme is analyzed theoretically and compared with other methods. The circuit is designed and simulated in standard 180 nm mixed mode CMOS technology. The minimum required supply voltage is 400 mV. A worst case temperature coefficient of 4 ppm/°C is achieved over 0-100°C temperature range. The reference voltage exhibits mean value of 169.37 mV with worst case deviation of ±1.35 mV across process corners and temperature range of 0-100°C. Achieved PSRR at 100 Hz and 1 MHz is -86 dB and -30 dB, respectively.

Published in:

Quality Electronic Design (ASQED), 2013 5th Asia Symposium on

Date of Conference:

26-28 Aug. 2013