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A 128-phase delay-locked loop with cyclic VCDL

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2 Author(s)
Chien-Hung Kuo ; Dept. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei, Taiwan ; Yu-Chieh Ma

A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.

Published in:

Quality Electronic Design (ASQED), 2013 5th Asia Symposium on

Date of Conference:

26-28 Aug. 2013