By Topic

Retiming edge-triggered circuits under general delay models

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lalgudi, K.N. ; Intel Corp., Hillsboro, OR, USA ; Papaefthymiou, M.C.

The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. For relatively simple delay models, an optimal retiming of a given circuit can be computed in polynomial time. Under more comprehensive delay models, however, the retiming problem is solved by resorting to branch-and-bound techniques. In this paper, we investigate retiming under delay models that encompass load-dependent gate delays, register delays, interconnect delays, and clock skew. For the most general of our delay models, we express the retiming problem as a set of integer linear programming (ILP) constraints that can be solved using ILP techniques. For less general delay models, which encompass circuits with monotonic clock skews and load-dependent gate delays, we give an integer monotonic programming formulation for the retiming problem and an asymptotically efficient retiming algorithm. Our algorithm re-times any given edge-triggered circuit to achieve a specified clock period in O(V3 F) steps, where V is the number of combinational logic gates in the circuit and F is a constant no greater than the circuit's register count. We have implemented our algorithms in DELAY, a software tool for optimizing synchronous circuits, and have evaluated their performance on benchmark circuits

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:16 ,  Issue: 12 )