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A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm

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2 Author(s)
Yeong-Kang Lai ; Dept. of Electron. Eng., Chang Gung Univ., Taiwan ; Liang-Gee Chen

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search blockmatching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates

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Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:8 ,  Issue: 2 )