By Topic

Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
C. S. Murthy ; IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA ; M. Gall

This paper describes the first study of the complete sequence from process simulation to circuit performance and the corresponding sensitivities for 0.25-μm technology. This is made possible by a combination of physically based process models and a systematic calibration involving SIMS, one-dimensional (1-D), and two-dimensional (2-D) device characteristics. Simulated nFET and pFET characteristics match hardware (HW) within 5-10% for both long-channel and nominal length devices. Simulated ring-oscillator performance is in good agreement with HW data. Sensitivities of device characteristics and the inverter gate delay to process variations (within 10%) are quantified. These investigations establish the correlation between process variations and circuit performance

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:16 ,  Issue: 11 )