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An analog VLSI implementation of a feature extractor for real time optical character recognition

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3 Author(s)
Bo, G.M. ; Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy ; Caviglia, D.D. ; Valle, M.

The architecture, the design, and the analog very large scale integration (VLSI) implementation of a feature extractor chip for optical character recognition (OCR) systems are described. The chip extracts a set of 112 feature values coded by current signals from a 32×24 digital pixel matrix, representing the input character. Such features are applied to a classifier (for example, a neural classifier) performing the recognition task. The measurements performed on that chip confirm its functionality. The chip can be used with a segmented and nonsegmented string of characters. A throughput of about 140 kChar/s is achieved for the segmented case, while a throughput of about 450 kChar/s is achieved for the nonsegmented case. The OCR architecture has been functionally validated. A set of numerical handwritten characters has been processed by the chip and the measured output features (after a normalization operation) have been used as input for neural network classifier; implemented by a software simulator which performs the recognition task. The resulting classification error rate (4.3%) has been successfully compared with those obtained by a high level model of this chip, and the results validate the entire architecture

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 4 )

Date of Publication:

Apr 1998

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