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An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture

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2 Author(s)
Aayush Prakash ; Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada ; Hiren D. Patel

This paper presents a static instruction scratchpad memory allocation scheme for the precision timed architecture (PRET). Since PRET provides timing instructions to control the temporal execution of programs, the objective of the allocation scheme is to ensure that the explicitly specified temporal requirements are met. Furthermore, this allocation incorporates the timing requirements from the multiple hardware threads of the PRET architecture. We formulate the allocation problem as an integer-linear programming problem, and we implement a tool that takes compiled ARMv4 binaries, constructs a timing-requirements-aware control-flow graph, performs a WCET analysis and SPM allocation, and rewrites the binaries with the allocation. We evaluate our approach using a modified version of the Malardalen benchmarks to show the benefits of the proposed approach. We also present a UAV benchmark derived from the PapaBench benchmark.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:32 ,  Issue: 11 )