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Test Time Reduction in EDT Bandwidth Management for SoC Designs

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6 Author(s)
Janicki, J. ; Fac. of Electron. & Telecommun., Poznan Univ. of Technol., Poznan, Poland ; Kassab, M. ; Mrugalski, G. ; Mukherjee, N.
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This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:32 ,  Issue: 11 )