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Multi-level factorisation technique for pass transistor logic

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3 Author(s)
Jaekel, A. ; Sch. of Comput. Sci., Windsor Univ., Ont., Canada ; Bandyopadhyay, S. ; Jullien, G.A.

Discusses a technique of using multi-level logic synthesis to design pass transistor logic (PTL) based on algebraic factorisation. Techniques already applied to conventional AND-OR type networks are shown to be not useful for factorisation of PTL networks. Starting with the set of all prime pass implicants, the steps of selecting a cover and factorising a function, using a greedy heuristic, are combined. From many examples using MCNC benchmark circuits, the algorithm achieves a considerable improvement (an average of 14% and up to 50% savings) over PTL circuits obtained from conventional two-level design methods

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:145 ,  Issue: 1 )

Date of Publication:

Feb 1998

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