By Topic

Towards a compiler/runtime synergy to predict the scalability of parallel loops

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chatzopoulos, G. ; Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece ; Kourtis, K. ; Koziris, N. ; Goumas, G.

Large classes of applications fail to scale well in CMPs due to contention in the memory subsystem. Assigning full core capacity to such applications is a clear resource waste. To support efficient and power-aware resource allocation policies, we need a prediction mechanism to provide information about the potential scalability of an application. In this paper we take an initial step towards building a scalability predictor, based on the utilization of information collected both during compile and runtime. Our approach is applied separately to each parallel-for region in the program and calculates an on-chip to off-chip activity ratio Sr, which then is associated to the scalability of the region (maximum speedup) with linear regression. Experimental results on two architectures using the Polybench suite demonstrate that our prediction model exhibits a good accuracy in predicting the scalability of various parallel-for regions.

Published in:

Multi-/Many-core Computing Systems (MuCoCoS), 2013 IEEE 6th International Workshop on

Date of Conference:

7-7 Sept. 2013