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Si photonic devices are sensitive to the change in refractive index on the Si-on-insulator (SOI) platform. One of the critical limitations in the compact 3D photonic integration circuit is the through-Si-via (TSV)-induced stress, which affects the performances of Si photonic devices integrated in interposer. We build a model to analyze and simulate the wavelength shift of the ring resonator caused by the effective-refractive-index change in the waveguide, arising from TSV-induced stress in the SOI interposer. Double-cascaded ring resonators integrated in the SOI interposer were fabricated and their wavelength shifts were characterized. The results show that the resonance wavelength shift on the order of 0.1 nm can be caused by the TSV-induced stress for , where d and R are the distance between the TSV and the Si waveguide, and the radius of TSV, respectively. This shift results in performance deviation from the target of design. Finally, this paper proposes a TSV keep-out-zone for the Si photonic ring resonator and a compact scaling of the SOI photonics interposer.