A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

In this short paper, we present a new integrated synthesis and partitioning approach for multiple-field programmable interconnect chips (FPICs) implementations from register-transfer (RT) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and partitioning method which fully exploits the design structural hierarchy by decomposing RTL components into sets of logic subfunctions. This allows the partitioner to place portions of components into FPGA partitions. Experimental results on a number of benchmarks and industrial designs show that our approach achieves significant improvement in FPGA configurable logic block (CLB) and I/O-pin utilizations compared to that produced using a traditional multiple-FPGA partitioning method