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Reconfigurable Processor for Energy-Efficient Computational Photography

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5 Author(s)
Rithe, R. ; Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA ; Raina, P. ; Ickes, N. ; Tenneti, S.V.
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This paper presents an on-chip implementation of a scalable reconfigurable bilateral filtering processor for computational photography applications such as HDR imaging, low-light enhancement, and glare reduction. Careful pipelining and scheduling has minimized the local storage requirement to tens of kB. The 40-nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.5 V. The test chip processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared with software implementations on recent mobile processors.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 11 )