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A high-performance VLSI architecture for MAPS criterion motion estimation

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4 Author(s)
Ming-Der Shieh ; Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Ming-hwa Sheu ; Yu-Chin Hsu ; Jia-Lin Sheu

In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the fast algorithm presented. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.

Published in:

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on  (Volume:2 )

Date of Conference:

3-6 Aug. 1997