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Power dissipation and reliability are important issues in the design of high performance digital VLSI circuits. Power dissipation and reliability are strongly related to switching activity in the circuit. An estimate of maximum switching activity is necessary for the design of reliable circuits. The problem of estimating maximum switching activity even under a zero gate delay model is intractable. In this paper, we present an algorithm to obtain an upper bound on the maximum transition count over all possible input vectors under a zero gate delay model.