Cart (Loading....) | Create Account
Close category search window
 

Design verification by concurrent simulation and automatic comparison

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Taekyoon Ahn ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Kiyoung Choi

Verifying a synthesized hardware design is a tedious and time consuming task because the existing methods need designer's efforts of checking the simulation results. We propose a new verification method which compares automatically the simulation results obtained for two designs: one before synthesis and one after synthesis. The two simulations, one for each design, run concurrently, comparing each pair of matching nets. The inconsistency is reported as soon as possible without necessarily completing the simulation run. Experimental results show that our method detects design errors earlier and easier than the existing methods.

Published in:

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on  (Volume:2 )

Date of Conference:

3-6 Aug. 1997

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.