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Improving two-level logic minimization technique for low power driven multilevel logic re-synthesis

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2 Author(s)
Hoon Choi ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Seung Ho Hwang

In this paper, we revisit the two-level logic minimization technique for low power driven multi-level logic resynthesis. It extended the algorithms used in ESPRESSO, by adding the heuristics that bias the minimization toward lowering the power dissipation in the circuit. Though the method showed good results, it did not consider the non-linear change of the cube activity that happens as the cube is expanded/reduced by eliminating/adding some literals. In this paper, for the first time in our knowledge, we show the above problem of the previous method and propose the methods to solve it. The experimental results show the validity of our proposed methods.

Published in:

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on  (Volume:2 )

Date of Conference:

3-6 Aug. 1997