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This paper presents a 1-GHz ΔΣ fractional-N PLL with a noise-filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR filtering for the quantization noise from the ΔΣ modulator. The implemented PLL in 0.13- μm CMOS consumes 16.8 mW and shows a reduction of the phase noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed filtering technique achieves an in-band noise of -106 dBc at 100 kHz and an out-of-band noise of -107.5 dBc at 6 MHz.