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A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection

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2 Author(s)
Shih-Yuan Kao ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shen-Iuan Liu

A 10-Gb/s adaptive parallel receiver with joint crosstalk canceller (XTC) and decision-feedback equalizer (DFE) is presented. A differentiator-based XTC and a one-tap DFE are adapted to cancel far-end crosstalk (FEXT) and inter-symbol interference (ISI), respectively. When the lengths of the coupled microstrip lines change, an FEXT detector measures and compares the powers of FEXT and XTC to digitally update the XTC coefficient. Then, an ISI detector measures and compares the powers of the received data and recovered data to digitally update the DFE coefficient. This adaptive parallel receiver was fabricated in a 40-nm CMOS technology. The maximum power consumption is 17.55 mW from a 1.3-V supply, and the core area occupies 0.0352 mm2. For a 10-Gb/s PRBS of 27-1 passing through 15-in FR4 printed-circuit-board traces with 8-mil spacing, the measured rms and peak-to-peak jitter of recovered data are 5.56 and 30.2 ps, respectively. The measured bit error rate is less than 10-12. The measured total calibration time is 2.424 μs.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 11 )