By Topic

Comments on "Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters"

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. G. Dempster ; Dept. of Electron. Syst., Univ. of Westminster, London, UK ; M. D. Macleod

For the original paper see ibid., vol. 42 p. 453-460 (July 1995). In the aforementioned paper by D. Li, a method of designing integer multipliers that uses fewer adders than canonic signed-digit (CSD) coding was described. This method is claimed by the author to be optimal, i.e., it produces a multiplier with the least possible adders. The commenters claim that they have presented a similar method, implemented using the MAG algorithm, to perform the same task, which was shown to be optimal. Comparing the two techniques shows that Li's method is not necessarily optimal. Both methods perform an exhaustive search over a set of multiplier configurations. In the commenters' paper, they described these configurations in terms of graphs. It is said that this method proves to be quite useful in that it becomes easy to describe the cases not covered by Li's algorithm. It is stated that the algorithm proposed by Li is suboptimal because: 1) graphs produced using fundamentals (intermediate vertices) of lower cost graphs are not considered; 2) tree-structured graphs are not considered; 3) right shifts (divide-by-two) are not allowed, causing some multipliers to require too many adders.

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:45 ,  Issue: 2 )