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Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

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2 Author(s)
R. R. Manikandan ; Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India ; Bharadwaj Amrutur

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13- μm CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:60 ,  Issue: 12 )