Cart (Loading....) | Create Account
Close category search window

A DC method for measuring all the gate capacitors in MOS devices with atto-farad resolution

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Manku, T. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; MacEachern, L.

In this paper we present a new methodology for measuring all the intrinsic gate capacitors (i.e., gate-source, gate-drain, and gate-bulk) in a MOS device using a DC measurement scheme. The structure consists of two matched MOSFET's, one of which has a reference capacitor attached to its gate. The test structure was fabricated and the results show a resolution in the atto-farads range. The test structures use charge coupling to measure the gate capacitors

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:11 ,  Issue: 1 )

Date of Publication:

Feb 1998

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.