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Accurate area and delay estimation from RTL descriptions

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3 Author(s)
Srinivasan, A. ; Mentor Graphics Corp., San Jose, OR, USA ; Huber, G.D. ; LaPotin, D.P.

In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design. The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-fit polynomial area and delay models on the resulting technology-independent representation. The estimation techniques were incorporated into a tool called QUEST. QUEST was used by designers of a large commercial CPU to obtain quick feedback on the area and delay impart of behavioral modifications, resulting In significant savings in design schedule.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 1 )