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Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

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3 Author(s)
Guerra, L.M. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Potkonjak, M. ; Rabaey, J.M.

In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including: (1) design for fault tolerance against permanent faults, (2) design for Improved manufacturability, and (3) design of application specific programmable processors (ASPPs)-processors designed to perform any computation from a specified set on a single implementation platform. This paper focuses on design techniques for efficient built-in self-repair (BISR), and thus directly addresses the former two applications. Previous BISR techniques have been based on replacing a failed module with a backup of the same type. We present new heterogeneous BISR methodologies which remove this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behavioral-level synthesis to explore the design space. Two behavioral synthesis techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental results verify the effectiveness of the approaches.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 1 )