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Maximum power estimation for CMOS circuits using deterministic and statistical approaches

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2 Author(s)
Wang, C.-Y. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Roy, K.

Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent input-pattern dependence of the problem, it is impractical to conduct an exhaustive search for circuits with a large number of primary inputs. Hence, the practical approach is to generate a tight lower bound and an upper bound for maximum power dissipation within a reasonable amount of central processing unit (CPU) time. In this paper, instead of using the traditional simulation-based techniques, we propose a novel approach to obtain a lower bound of the maximum power consumption using automatic test generation (ATG) technique, Experiments with MCNC and ISCAS-85 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulation-based techniques. In addition, a Monte Carlo-based technique to estimate maximum power dissipation is described. It not only serves as a comparison version for our ATG approach, but also generates a metric to measure the quality of a lower bound from a statistical point of view.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 1 )

Date of Publication:

March 1998

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