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The continuing development of smaller electronic devices into the nanoelectronic regime offers great possibilities for the construction of highly parallel computers. This paper describes work designed to discover the best ways to take advantage of this opportunity. Simulated results are presented which indicate that improvements in clock rates of two orders of magnitude, and in packing density of three orders of magnitude, over the best current systems, should be attainable. These results apply to the class of data-parallel computers, and their attainment demands modifications to the design which are also described. Evaluation of the requirements of alternative classes of parallel architecture is currently under way, together with a study of the vitally important area of fault-tolerance.