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A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation

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3 Author(s)
J. A. Davis ; Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA ; V. K. De ; J. D. Meindl

For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size

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IEEE Transactions on Electron Devices  (Volume:45 ,  Issue: 3 )