By Topic

A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
N. Kusayanagi ; Electron. Lab., Yokogawa Electr. Corp., Tokyo, Japan ; T. Choi ; M. Hiwatashi ; M. Segami
more authors

A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-μm double-poly, double-metal (DPDM) CMOS process technology. In the analog-to-digital conversion, a time-interleaved successive approximation architecture effectively enables both 25 Ms/s 8-b and 10 Ms/s 10-b operation. The input signal conditioner consists of a variable gain amplifier (VGA) and a second-order programmable low-pass filter (LPF) using folded-cascode structures with current feedback circuits. The overall gain is externally controllable from 12 dB to 38 dB, and the bandwidth is programmable at 500 kHz, 5 MHz, and 25 MHz. The chip consumes 340 mW at the 25 Ms/s operating condition and less than 8 mW in the power-down mode from a single 5 V supply

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 3 )