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System architecture of an adaptive reconfigurable DSP computing engine

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3 Author(s)
An-Yeu Wu ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; Liu, K.J.R. ; Raghupathy, A.

In this paper, we present the system architecture of an adaptive reconfigurable DSP computing engine for numerically intensive front-end audio/video communications. The proposed system is a massively parallel architecture that is capable of performing most low-level computationally intensive data processing including finite impulse response/infinite impulse response (FIR/IIR) filtering, subband filtering, discrete orthogonal transforms (DT), adaptive filtering, and motion estimation for the host processor in DSP applications. Since the properties of each programmed function such as parallelism and pipelinability have been fully exploited in this design, the computational speed of this computing engine can be as fast as ASIC designs that are optimized for individual specific applications. We also show that the system can be easily configured to perform multirate FIR/IIR/DT operations at negligible hardware overhead. Since the processing elements are operated at half of the input data rate, we are able to double the processing speed on-the-fly based on the same system architecture without using high-speed/full-custom circuits. The programmable/high-speed features of the proposed design make it very suitable for cost-effective video-rate DSP applications

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:8 ,  Issue: 1 )

Date of Publication:

Feb 1998

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