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Implementing C designs in hardware: a full-featured ANSI C to RTL Verilog compiler in action

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2 Author(s)
Soderman, D. ; CompiLogic Corp., San Jose, CA, USA ; Panchul, Y.

The usage of a new full-featured ANSI C to synthesizable RTL Verilog compiler for implementing system-level algorithms in hardware is described. The compiler automatically creates multiple Verilog state machines for loops, on-chip register and arithmetic macros, and external memory interfaces. A two-pass compile interfacing with a synthesis tool allows insertion of registers and wait states to balance propagation delays for maximum performance. This design methodology is demonstrated using several compression-decompression, prime number, and sorting algorithms. Compiled RTL Verilog designs have been synthesized into FPGAs and ASICs. The compression-decompression algorithm executes in nearly one quarter the clock cycles using hardware versus software on a PentiumPro. This cycle efficiency is due to variable storage in simple registers, clock packing techniques, and functional level parallelism. Efficient clock packing is demonstrated with a prime number generator algorithm which executes in 25x fewer clock cycles compared to Pentium software execution

Published in:

Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International

Date of Conference:

16-19 Mar 1998