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Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

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7 Author(s)
Xiaoming Chen ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Hong Luo ; Yu Wang ; Yu Cao
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Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.

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Circuits, Devices & Systems, IET  (Volume:7 ,  Issue: 5 )