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Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 μm

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3 Author(s)
Nayak, D. ; Adv. Micro Devices Inc., Sunnyvale, CA, USA ; Hao, Ming‐Yin ; Hijab, R.

During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 μm-generation to 0.13 μm-generation technology

Published in:

Integrated Reliability Workshop Final Report, 1997 IEEE International

Date of Conference:

13-16 Oct 1997