Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 /spl mu/m

During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 /spl mu/m-generation to 0.13 /spl mu/m-generation technology.